Summary
The technology is being developed for faster and more efficient next-generation computing
Findings of the study have been published in top-tier journals
Researchers at Indian Institute of Technology (IIT) Guwahati have been working on ways to develop secure and reliable integrated circuits (ICs) at the institute’s Automation, Verification and Security (AVS) Lab to strengthen the electronics manufacturing ecosystem in India with faster and more efficient computing technology.
The study focuses on characteristics of the automated electronics design process such as synthesis, verification and security. It has been funded by Core Research Grant (CRG), Early Career Research (ECR), Interdisciplinary Cyber-Physical Systems (ICPS) grants from the Department of Science & Technology and a Research Fellowship from Intel (India). Findings of the study have been published in journals and conferences of the Institute of Electrical and Electronics Engineers (IEEE).
The published paper has been authored by Qualcomm Faculty Award 2021 recipient Chandan Karfa, associate professor, Department of Computer Science & Engineering, IIT Guwahati. The paper has been co-authored by Karfa’s research students Priyanka Panigrahi, Nilotpola Sarma, Mohammed Abderehman, Debebdara Senapati and Surajit Das. IIT Guwahati alumni Ramanuj Chouksey, Jay Oza, Yom Nigam, Abdul Khader and Jayprakash Patida also contributed to the research
An ever-increasing computational demand has given rise to the need for application-specific processors which can perform better than the current central processing units (CPUs). The computing power improvements of multicore processors that are used today continue to be insufficient.
Discussing the importance of the research, Karfa said, “A promising technology to improve computational efficiency is hardware accelerators. In hardware acceleration, specific tasks can be offloaded to dedicated hardware instead of being performed by the CPU core of the system. For example, visualization processes may be offloaded onto a graphics card, thereby freeing the CPU to perform other tasks.”
The approach by the research team emphasised hardware acceleration specifications, which are often written in high-level languages like C/C++ and are converted to hardware code in a process called High-Level Synthesis (HLS). Several stringent validation steps are required as the complex conversion process and HLS translation introduces the possibility of bugs in the design. The team developed a faster and simpler tool instead of RTL simulators for the HLS verification.
“We have developed two tools to validate the HLS process. One is FastSim, an RTL simulator that is 300 times faster than existing commercial simulators. The other is DEEQ, which is an automated C to RTL equivalence checking tool for HLS verification. There is no other tool in the market with similar features,” Karfa added.
A technology called HOST was also developed by the team to protect ICs from Internet Protocol (IP) theft during the design cycle.
The study by the IIT Guwahati team is of major significance as there is an increasing demand for hardware accelerators in disruptive areas such as Internet-of-Things (IoT), embedded and cyber-physical systems, machine learning and image processing applications. Along with the Centre’s recent approval of a Rs 76,000-crore scheme to boost semiconductor manufacturing, the study by IIT Guwahati promotes self-sufficiency in chip design.
Last updated on 11 May 2022
